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ISL6884
Data Sheet March 9, 2006 FN9265.0
CCFL Brightness Controller
ISL6884 controls Pulse Width Modulated Dimming for up to 8 inverters to supply power to up to 40 Cold Cathode Fluorescent Lamps (CCFL) for back lighting in large LCD displays. The ISL6884 brightness controller provides an I2C interface for dimming control, enable, status, and brightness balance. The duty cycle of all 8 DPWM outputs is adjusted with a Master Brightness Control register. The duty cycle of each of the 8 DPWM outputs can be offset from the master brightness to adjust for uniform brightness. The PWM dimming frequency can be set by an internal, adjustable oscillator or synchronized to an external source to minimize interference with video. ISL6884's slave address is: * 1101_1111 for reading * 1101_1110 for writing
Features
* Wide Supply Voltage Range of 3.0V to 5.5V * Dimming - I2C dimming control input - PWM dimming can be synchronized to an external source or set by an internal, adjustable oscillator. - 8 channel dimming allows the user to balance the brightness of the CCFL lamps via I2C control - User programmable fault time out * User Programmable Fault Time Out * I2C Status Output * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6884 (20 LD SSOP) TOP VIEW
LAMP_ON 1 TESTEN 2 20 VDD 19 REGCAP 18 DPWM_8 17 DPWM_7 16 DPWM_6 15 DPWM_5 14 DPWM_4 13 DPWM_3 12 DPWM_2 11 DPWM_1
Ordering Information
PART NUMBER ISL6884IAZ (See Note) ISL6884IAZ-T (See Note) TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld SSOP (Pb-free) PKG. DWG. # M20.15
GNDPLL 3 PLL1 4 EN 5 DPWM_SYNC 6 OSCTEST 7 SCL 8 SDA 9 GND 10
20 Ld SSOP Tape M20.15 and Reel (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6884 Block Diagram
VDD GND EN
I2C ENABLE
fault timer BGREF POR 2.5V REG
REGCAP
ENAB
STATUS
LAMP ON
DPWM SYNC PLL1 GNDPLL
PWM DIMMING PLL 8 CH DPWM GEN
OSC
DPWM_8 DPWM_7 DPWM_6 DPWM_5 DPWM_4 DPWM_3 DPWM_2 DPWM_1
8
BRIGHTNESS
SDA SCL
I2C interface
STATUS ENABLE (I2C)
TESTEN OSCTEST
CCFL Brightness Controller
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ISL6884 Simplified System Diagram - Central Controller and Multiple Local Controllers
ISL6884 CENTRAL CONTROLLER
DPWM 4 DPWM 3 DPWM 2 DPWM 1
DPWM ISL6882 LOCAL CONTROLLER DRIVE IFB VFB PHASE MODULATION OUT DPWM ISL6882 LOCAL CONTROLLER DRIVE IFB VFB PHASE MODULATION OUT DPWM ISL6882 LOCAL CONTROLLER DRIVE IFB VFB PHASE MODULATION OUT
SCL SDA
SYSTEM I2C MASTER
CCFL CCFL CCFL DRIVE ISL6883 DRIVER PM IN
CCFL CCFL CCFL DRIVE ISL6883 DRIVER PM IN
CCFL CCFL CCFL DRIVE ISL6883 DRIVER PM IN
FI ON C
EN D
L IA T
DPWM ISL6882 LOCAL CONTROLLER
CCFL DRIVE IFB VFB CCFL CCFL DRIVE ISL6883 DRIVER PM IN
PHASE MODULATION OUT
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ISL6884 ISL6884 Application Schematic
external hardware enable LAMPON output from ISL6882 VDD
LAMP_ON TESTEN GNDPLL PLL1 EN 1uF 2200 DPWM_SYNC OSCTEST SCL SDA GND 0.47uF 73.2K 0.1uF to the system master, other I2C devices and pull up resisters 1 2 3 4 5 7 8 9 10 20 19 18 17 16 14 13 12 11 VDD REGCAP DPWM_8 DPWM_7 DPWM_6 DPWM_5 DPWM_4 DPWM_3 DPWM_2 DPWM_1
Use these parts to adjust the internal DPWM oscillator frequency
3300
6 ISL6884 15
to DPWM dimming inputs to up to 8 ISL6882
This is the LPF for the DPWM PLL
1uF
1uF
0.01uF
external signal to sync DPWM
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ISL6884
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Input/Output Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Thermal Information
Thermal Resistance (Typical, Notes 1) 20 Ld SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA (C/W) 110
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40C to 85C Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125C Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
Thermal Information
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER POWER ON RESET VDD Rising VDD Falling POR Hysteresis VOLTAGE REGULATOR Regulated Voltage
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PORrising PORfalling PORhyst
2.4 2.2 -
2.7 2.5 200
3.0 2.7 -
V V mV
Vreg
External Capacitor = 1F, ESR<1
2.3
2.5
2.7
V
LOGIC LEVEL INPUTS (EN, DPWM_SYNC, LAMPON) V In High V In Low Hysteresis Input Current VIHLOGIC VILLOGIC Vhyst I_IN Vin = VDD Vin = 0V I2 C V In Low V In High Schmitt Trigger Input Hysteresis V Out Low SDA, SCL Rise Time SDA, SCL Fall Time VIL VIH Vhys VOL Trise_I2C Tfall_I2C I in low = 3mA Cload = 200pF Rpullup = 1700, 30%-70% Cload = 200pF Rpullup = 1700, 30%-70% 0.7*VDD 0.05*VDD 300 0.3*VDD 0.4 300 V V V V ns ns 2.6 140 10 -10 0.8 V V mV nA nA
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ISL6884
Electrical Specifications
PARAMETER DPWM DPWM PLL Free Run Frequency DPWM PLL Lock Frequency Lock Time DPWM Duty Cycle DPWM Duty Cycle DPWM Duty Cycle DPWM Output High DPWM Output Low DPWM Rise Time DPWM Fall Time NOTE: 2. Master enable (0X2B) = 01, channel enable (0X2C) = FF, all other registers in default mode ffreerun flock Tlock DPWMDCmin BRT_M = 00hex (Note 3) DPWMDCmid BRT_M = 7Fhex (Note 3) DPWMDCmax BRT_M = FFhex (Note 3) VOH VOL Trise_DPWM Tfall_DPWM IOH = 2mA IOL = 2mA Cload = 200pF Cload = 200pF 120 3 49 98 0.7*VDD 160 160 150 4 50 200 5 51 100 0.3*VDD 500 500 Hz Hz ms % % % V V ns ns Recommended Operating Conditions, Unless Otherwise Noted (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Pin Description
VDD - Power input for digital systems. All functions are disabled unless this pin exceeds 3V (see Power On Reset specs). A 0.01F decoupling cap should be placed between VDD and GND with the shortest possible traces. GND - Ground for digital systems. REGCAP - An external 1F capacitor to decouple the internal 2.5V regulator. EN - Logic level input signal. Voltage at this pin above a threshold ENables circuit operation. DPWM SYNC - A logic level input signal. The dimming PWM frequency oscillator will synchronize to this signal (if present). If no signal is present at this pin, the internal DPWM oscillator will free run at approximately 160Hz. PLL1 - Analog input. An RC network on these pins sets the loop response of the DPWM Phase Locked Loop. A voltage source or resister divider at this pin will set the DPWM frequency. See the graph below for approximate frequency vs voltage at PLL1.
220 DPWM Frequency (Hz) 200 180 160 140 120 100 80 60 0.5 0.7 0.9 1.1 1.3 Voltage at PLL1 (V) F_DPWM=V_PLL1*160+8 measured
GNDPLL - A separate ground terminal for the PLL. Filter and bias components on PLL1 should be connected to this ground with the shortest possible traces. This pin is also connected to the system ground with a trace that is not critical. DPWM 1:8 - Logic level outputs that control the analog and PWM dimming of each of 8 ISL6882s. The duty cycle of the DPWM signals range from 4% (minimum brightness) to 100% (maximum brightness). A low pass filter in the inverter Controller converts the DPWM duty cycle to a DC voltage that performs 3:1 analog dimming. The combined dimming range is 100:1. The dimming value is set by I2C registers. LAMP_ON - A logic level input signal. A high level on the pin indicates that all lamps are ON and operating normally. A low level at this pin indicates that at least one of the lamps is either not ignited or out of the circuit. When this pin is low, the fault timer runs. When this pin is high, the fault timer is reset. Because this is a high impedance line that may be routed near sources of EMI, it is recommended that a 10K resister is placed in series between the LAMP_ON pin and all other circuits. SDA, SCL - Logic level input/output signals. SDA is the I2C data line and SCL is the I2C clock line. The ISL6884 receives data via I2C to enable or disable the inverters, set dimming for each channel, and set the number of channels. System status can be read via I2C. TESTEN and OSCTEST - These pins are used for internal tests. They should be left unconnected in normal operation.
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ISL6884 I2C Register Description
Register addresses and default values are given in the following Register Description Table. I2C Slave Address - ISL6884's slave address is: * 1101_1111 for reading * 1101_1110 for writing BRT_M - Master Brightness Control input. This register controls the duty cycle of al 8 DPWM outputs. BRT_OS[1..8] - Brightness offset. These registers allow the system designer to increase or decrease the duty cycle of individual channel to equalize the brightness of all lamps in a system. Note: Value is stored as 2's complement number. MSTR_EN - Master Enable, This signal is AND'ed with the EN pin to create the enable for the PWM dimming output. If this bit OR the EN pin is low the DPWM outputs are held low. CH_EN - Individual Channel Enables for each DPWM output. If only DPWM 1, 3, 5 and 7 are to be used, CH_EN bits 1, 3, 5, and 7 should be set to 1 and bits 2, 4, 6, and 8 should be set to 0. FLT_TOUT - Fault Timer Time Out Setting. This register controls the response of the ISL6884 to a logic low input on the LAMPON pin (indicating that one or more lamps is NOT ON). A value between 0X01 and 0XFF in the FLT_TOUT register will set the time that ISL6884 will operate with a low signal at the LAMPON pin (fault time out). The adjustment range is from less than 0.1 second to approximately 2 seconds. The power on reset default time out is 1 second. After a fault time out, all DPWM outputs are latched low until power is cycled. If FLT_TOUT is set to 0X00, ISL6884 will not time out and will continue to operate even with a low signal at the LAMPON pin. STATUS - indicates the status of the Time out Fault, LAMPON input signal and ENABLE (MSTR_EN AND EN pin).
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ISL6884 Register Description Table
Register Descriptions:
NOTES:
1. sb denotes sign bit for 2's compliment numbers. 2. The second row shows the register's default value loaded at Power On Reset.
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS) WORD NAME BYTE ADDRESS POR BRT_M 0x00 POR brt_os1 0x01 POR brt_os2 0x02 POR brt_os3 0x03 POR brt_os4 0x04 POR brt_os5 0x05 POR brt_os6 0x06 POR brt_os7 0x07 POR brt_os8 0x08 POR mstr_en 0x2a POR ch_en 0x2b POR flt_tout 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB LABEL POR VALUE BIT 6 LABEL POR VALUE BIT 5 LABEL POR VALUE DESCRIPTION BIT 4 LABEL POR VALUE BIT 3 LABEL POR VALUE BIT 2 LABEL POR VALUE BIT 1 LABEL POR VALUE LSB LABEL POR VALUE
Brightness Magnitude Setting b7 0 b6 0 b5 1 b4 1 b3 1 b2 1 b1 1 b0 1
Brightness Offset for Light Sensor 1. Note: Value is stored as 2's complement number sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 2. Note: Value is stored as 2's complement number. sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 3. Note: Value is stored as 2's complement number sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 4. Note: Value is stored as 2's complement number. sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 5. Note: Value is stored as 2's complement number sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 6. Note: Value is stored as 2's complement number. sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 7. Note: Value is stored as 2's complement number. sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Brightness Offset for Light Sensor 8. Note: Value is stored as 2's complement number. sb 0 b4 0 b3 0 b2 0 b1 0 b0 0
Master Enable, This signal is AND'ed with the en pin to create the enable for the PWM dimming output. mstr_en 0
Individual Channel Enables for each DPWM output. b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0
Fault Timer Time Out Setting.
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ISL6884
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS) (Continued) WORD NAME BYTE ADDRESS POR 0x2c POR CM 0x2d POR i2c_suh _pres 0x2E POR i2c_scl _hpres 0x2f POR i2c_scl_ lpres 0x30 POR i2c_bfree 0x31 POR i2c _stretch 0x32 POR toc_spd _ctrl 0x33 POR toc_spd _ctrl 0x34 POR toc_spd _ctrl 0x35 POR dc_max 0x36 POR dc_min 0 0 0 0 0 Time Out Counter Speed Control. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior b15 1 b14 1 b13 1 b12 0 b11 0 b10 1 b9 1 b8 1 0 0 0 0 0 0 0 Time Out Counter Speed Control. See I2C Document for description Caution! Changing this register from its default value may result in unpredictable behavior b18 0 b17 0 b16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C Setup/Hold Preset Value. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 MSB LABEL POR VALUE b7 1 BIT 6 LABEL POR VALUE b6 0 BIT 5 LABEL POR VALUE b5 0 DESCRIPTION BIT 4 LABEL POR VALUE b4 0 BIT 3 LABEL POR VALUE b3 0 BIT 2 LABEL POR VALUE b2 0 BIT 1 LABEL POR VALUE b1 0 LSB LABEL POR VALUE b0 0
Maximum Fails Setting. This value determines how many consecutive I2C fails can occur before channel is faulted. b1 0 b0 1
I2C SCL High Time Preset Value. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior b5 0 b4 0 b3 0 b2 1 b1 0 b0 0
I2C SCL Low Time Preset Value. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior b5 0 b4 1 b3 0 b2 0 b1 1 b0 0
I2C Bus Free Time Value. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior b5 0 I2C Stretch Value. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior i2c_stretch 0 b4 0 b3 1 b2 0 b1 1 b0 1
Time Out Counter Speed Control. See I2C Document for description. Caution! Changing this register from its default value may result in unpredictable behavior b7 0 b6 0 b5 1 b4 1 b3 1 b2 0 b1 0 b0 0
Duty Cycle Maximum Setting. See DPWM Document for description Caution! Changing this register from its default value may result in unpredictable behavior b7 1 b6 1 b5 1 b4 1 b3 1 b2 1 b1 1 b0 1
Duty Cycle Minimum Setting. See DPWM Document for description. Caution! Changing this register from its default value may result in unpredictable behavior
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ISL6884
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS) (Continued) WORD NAME BYTE ADDRESS POR 0x37 POR pwm_ sync_sel MSB LABEL POR VALUE b7 0 BIT 6 LABEL POR VALUE b6 0 BIT 5 LABEL POR VALUE b5 0 DESCRIPTION BIT 4 LABEL POR VALUE b4 0 BIT 3 LABEL POR VALUE b3 1 BIT 2 LABEL POR VALUE b2 0 BIT 1 LABEL POR VALUE b1 0 LSB LABEL POR VALUE b0 1
PWM Sync Mode Select. PWM_SYNC_SEL = xxxxxx00: INTERNAL ONLY. DPWM frequency set by an internal oscillator. External DPWM_SYNC is ignored. PWM_SYNC_SEL = xxxxxx01: AUTOMATIC SYNC SELECT. DPWM frequency set by an external DPWM_SYNC signal if it is present or by the internal oscillator if no external signal is present. PWM_SYNC_SEL = xxxxxx10: EXTERNAL ONLY. DPWM frequency set by an external signal at DPWM_SYNC. No signal at DPWM_SYNC results in no DPWM output switching. pwm_sync _sel2 0 0 0 0 0 0 0 pwm_sync _sel1 1
0x38 POR pll_bypass pmp1 pmp0 0x39 POR 0 0 0 0 0
Bypass PLL bit = 1 forces DPWM frequency to an internal oscillator. Charge Pump Bit1. See Plan 9 CDR Document for description. Charge Pump Bit0. See Plan 9 CDR Document for description. Caution! Changing this register from its default value may result in unpredictable behavior pll_bypass 0 pmp1 0 pmp0 0
Mux Selection for test mode mux. If the part is in test mode, the decode of this value changes the following pins:mx_sel = 0: dpwm6, dpwm7, dpwm8 in functional mode. mx_sel = 1: dpwm6 = vco_out, dpwm7 = div512_out, dpwm8 = div64_clk. mx_sel = 2: dpwm6 in functional mode, dpwm7 = clk_d4, dpwm8 = dpwm_clk. Caution! Changing this register from its default value may result in unpredictable behavior 0x3A POR 0 0 0 0 mx_sel b3 0 b2 0 b1 0 b0 0
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ISL6884 I2C Bus General Description
Introduction
(Refer to Philips I2C Specification, Rev. 2.1) The I2C bus is a 2 wire communication bus for integrated circuits. I2C, I2C or IIC are commonly used instead of the formal name Inter-Integrated-Circuit bus. The 2 wires are the SCL (Serial CLock) and SDA (Serial DAta). All ICs on the bus are connected to the SCL and SDA lines. SCL and SDA pins on each device are bidirectional and can act as either inputs or open drain outputs. Which device is transmitting and receiving is determined by the bus protocol which will be described below.
VDD
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Refer to Figure 2.
SDA
SCL DATA LINE CHANGE STABLE OF DATA DATA VALID ALLOWED
I2C Slave
input
FIGURE 2. DATA VALIDITY
state machine, registers, memory, etc.
I2C Master
SCL control SDA control
input output input output
output input output
SCL control SDA control
Byte Format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB).
CPU
I2C Slave
input output input
SCL control SDA control
SCL
SDA
output
state machine, registers, memory, etc.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 3). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.) The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer.
to other slave devices
A typical I2C bus system is made of a `master' that initiates communication (usually a microprocessor) and one or more `slaves' that respond to commands from the master. Each slave has a device address. In a typical communication sequence, the master will initiate communication with a `start condition' followed by the address of one of the slave devices. The slave device must acknowledge that it recognizes its address. After receiving the acknowledge, the master will transmit one or more bytes of commands and data. If the slave device is an EEPROM the command is the address within the EEPROM that is to be read or written. If data is to be written to the EEPROM the master transmits it after the command.
SCL 1 SDA MSB START ACKNOWLEDGE FROM SLAVE 2 8 9
START and STOP Conditions
As shown in Figure 1, START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
FIGURE 3. ACKNOWLEDGE ON THE I2C BUS
SDA
SCL S START CONDITION P STOP CONDITION
FIGURE 1. START AND STOP WAVEFORMS
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SDA SCL SCL SCL SCL
bus idle start bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 2 bit 3 bit 3 bit 4 bit 4 bit 5 bit 5 bit 6 bit 6 bit 7 (MSB) bit 7 (MSB) start start bus idle bus idle
SDA
SDA
SDA
bus idle
start
bit 7 (MSB)
bit 6
bit 5
bit 4
110111
110111
110111
110111
bit 3
ISL6884 DEVICE ADDRESS
ISL6884 DEVICE WRITE ADDRESS
ISL6884 DEVICE WRITE ADDRESS
ISL6884 DEVICE WRITE ADDRESS
bit 2
1 0 0 0
bit 0 ( R / W ) ACK from ISL6884 ACK from ISL6884 ACK from ISL6884 bit 0 ( R / W ) WRITE bit 0 (LSB)
1
1
1
bit 1
bit 1
bit 1
bit 1
0
bit 0 ( R / W )
ACK from ISL6884
READING ONE REGISTER IN ISL6884
WRITING TO ONE REGISTER IN ISL6884
Below are typical transactions between the system master and the ISL6884.
WRITING N CONSECUTIVE REGISTERS TO ISL6884
READING CONSECUTIVE REGISTER FROM ISL6884
I2C Transactions Between the System Master and the ISL6884
12
bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) ACK from ISL6884 bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) ACK from ISL6884 bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 (MSB) bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) ACK from ISL6884 bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) ACK from ISL6884 REGISTER ADDRESS REGISTER ADDRESS REGISTER ADDRESS re-start bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 DATA WRITTEN TO THE REGISTER ADDRESS A DATA WRITTEN TO THE REGISTER ADDRESS
bit 7 (MSB)
bit 6
bit 5
bit 4
bit 3
NO ACK from MASTER tells ISL6884 to stop sending data
FIRST REGISTER ADDRESS A
bit 2
bit 1
bit 0 (LSB)
ACK from ISL6884
re-start
bit 7 (MSB)
bit 6
bit 5
bit 4
110111
110111
bit 3
ISL6884
ACK from MASTER
ISL6884 DEVICE READ ADDRESS ISL6884 DEVICE READ ADDRESS
bit 2
1 1
bit 0 ( R / W ) ACK from ISL6884 bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) DATA WRITTEN TO THE REGISTER ADDRESS A+1
1
bit 1
bit 1
ACK from ISL6884 bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) ACK from ISL6884
1
bit 0 ( R / W )
ACK from ISL6884
stop bus idle
bit 7 (MSB)
bit 6
bit 5
bit 4
bit 3
bit 2
DATA READ FROM THE REGISTER ADDRESS
DATA READ FROM REGISTER ADDRESS A NO ACK from MASTER tells ISL6884 to stop sending data stop bus idle
bit 1
bit 0 (LSB)
bit 7 (MSB) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (LSB) ACK from ISL6884
bit 7 (MSB)
bit 6
bit 5
DATA WRITTEN TO THE REGISTER ADDRESS A+n
bit 4
bit 3
bit 2
DATA READ FROM REGISTER ADDRESS A+n
bit 1 stop bus idle
bit 0 (LSB)
stop
FN9265.0 March 9, 2006
bus idle
ISL6884 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 h x 45 L GAUGE PLANE 0.25(0.010) M BM
M20.15
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1 A2 B C D
C
MILLIMETERS MIN 1.35 0.10 0.20 0.18 8.56 3.81 5.80 0.26 0.41 20 0 MAX 1.75 0.25 1.54 0.30 0.25 8.74 3.98 6.19 0.49 1.27 8 NOTES 9 3 4 5 6 7 Rev. 1 6/04
MIN 0.053 0.004 0.008 0.007 0.337 0.150 0.228 0.0099 0.016 20 0
MAX 0.069 0.010 0.061 0.012 0.010 0.344 0.157 0.244 0.0196 0.050 8
A1 0.10(0.004) A2
e
B 0.17(0.007) M C AM BS
E e H h L N
0.025 BSC
0.635 BSC
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN9265.0 March 9, 2006

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